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+--- Thread: Regd-Rule 12.6 and 12.7 (/showthread.php?tid=1142)
Regd-Rule 12.6 and 12.7 - Nasi - 23-01-2015
The following code is Auto generated code from Embedded Coder of Matlab Simulink.
Code:
tmp = Common_Signal_Process_DWork.UnitDelay_DSTATE_b[1] * ((int16_T)(16384 -
Common_Signal_Process_DWork.UnitDelay3_DSTATE_d));
/* Switch: '/Thrs~=4' incorporates:
* Product: '/Product1'
* Switch: '/Thrs~=3'
*/
rtb_Thrs5_idx_1 = (int16_T)((tmp >> 14) + ((tmp & 8192) != 0));
rtb_Thrs5_idx_2 = Common_Signal_Process_DWork.UnitDelay_DSTATE_b[2];
rtb_Thrs5_idx_3 = Common_Signal_Process_DWork.UnitDelay_DSTATE_b[3];
}rtb_Thrs5_idx_1 = (int16_T)((tmp >> 14) + ((tmp & 8192) != 0));
On the Highlighted code above, we are getting MISRA-C 12.6 and 12.7 Rule violations. How to remove this violation?
Re: Regd-Rule 12.6 and 12.7 - misra-c - 13-02-2015
Given the cast on the first line, we assume that "tmp" has a "signed short" or "signed int" type. "tmp & 8192" therefore violates rule 12.7.
The result of "((tmp & 8192) != 0)" is effectively Boolean and is used as an operand to "+", which therefore violates rule 12.6.
The MISRA-C Working Group can make no further comment as to how a particular auto-coder can be configured to avoid these violations, but perhaps other users may help you.